1. Field of the Invention
The present invention relates to an integrated circuit that enters input signals in synchronized with a clock, such as clock synchronized dynamic memory, and more particularly to synchronized dynamic memory and integrated circuits that can reduce power consumption during refresh operations implemented in response to refresh commands from the controller.
2. Description of the Related Art
A synchronized dynamic memory (SDRAM) enters commands, addresses, and write data and output read data in synchronized with a clock, to enable fast operation. The supplied clock is supplied to command, address, and data input-output buffers within memory. SDRAM, in synchronization with the leading edge of the clock, receives commands, addresses, and write data supplied from the memory controller and outputs read data.
In normal operation mode, a clock with a prescribed cycle is supplied and the SDRAM decodes commands supplied from the memory controller and, in response to commands, implements read, write, or refresh operations. In a refresh operation, a refresh command is supplied from the memory controller and a refresh operation is implemented for an internally generated refresh address. When there is no more access to memory, a prescribed command from the memory controller places SDRAM in power down mode so that it simply holds data. In power down mode, clock input is stopped and the input or output of commands, addresses, and data also stops.
In dynamic memory, refresh operations must be implemented regularly because the storage data of a memory cell is volatiled after a certain period. In normal operation mode, a refresh operation is implemented in response to a command from the memory controller. On the other hand, in power down mode, there is no command from the memory controller and a refresh operation is implemented in response to a refresh command issued internally. To enable these self-refresh operations, SDRAM contains an oscillator, which measures the refresh timing, and a refresh address counter. In power down mode, the oscillator generates a trigger signal after a certain period has passed, and, in response to this, a refresh command is issued internally and a refresh operation is implemented for the address indicated on the refresh counter.
Even when it is not in power down mode, when access to SDRAM is disabled and SDRAM is merely holding data, self-refresh operations can be repeatedly implemented.
On the other hand, in network Large Scale Integration (LSI) or image processing LSI, it is proposed that a logic circuit for the required data processing and an SORAM macro for recording large amounts of data during data processing be embedded in one LSI chip. A memory controller is built into such an embedded memory logic LSI and this is used to control the SDRAM macro.
Here, it is proposed that both when the SDRAM macro is operating normally or in power down mode, the memory controller shall manage the timing with which it is refreshed and shall supply refresh commands with the timing required for the SDRAM macro. This is because it is preferable that the controller in a chip manages all refresh operations for any DRAM macro included in the chip.
In the above memory embedded LSI, the embedded SDRAM macro does not contain the self-refresh function that is provided in a single SDRAM unit. In status in which data is held without access to memory, such as in power down mode, the refresh operation can not be performed in the embedded SDRAM. Therefore, in order to perform the refresh operation, the embedded SDRAM macro must be transferred to a normal mode to enter a refresh command. If the embedded SDRAM macro need to enter a refresh command during the power down mode, the SDRAM macro must input a clock from outside and input a command in synchronized with the clock. In this case, the external clock is distributed from the clock input buffer to internal input buffers for commands, addresses, and data.
However, in the power down mode having the refresh operation but not being accessed for read/write, despite the fact that addresses or data input or output need not to be input, the external clock is distributed to both the input and output buffers. When the capacity of memory is increased, the number of address input buffers increases and the number of data input-output buffers also tends to increase. Relatively long wiring and large transistor gate electrode capacities must be driven to distribute the external clock to these input buffers and this increases the power consumption.
Another problem is described below.
Conventional general purpose dynamic random access memory (DRAM) has a self-refresh function and therefore can execute a refresh operation within the chip. Because of this, conventionally, the supply of external clock signals is stopped when data is merely being held (in the so-called standby status), thus holding down the power consumption required in data hold status to a minimal value.
On the other hand, in devices in which DRAM is embedded with a logic circuit in the same chip (DRAM embedded logic circuit), the logic circuit controller cannot monitor the self-refresh function built into the DRAM and it is therefore not practical to build a self-refresh function into the DRAM. Accordingly, as explained above, in a DRAM combined logic circuit, in both normal operation and data hold statuses, it is preferable that the refresh operation is controlled from the memory controller without building a self-refresh function into the DRAM.
Here, in devices without such a self-refresh function, a refresh command is supplied during data hold operations and therefore a clock signal must be sent from outside the device. Therefore, power is consumed for the supply of the clock and the problem of increased power consumption during data hold operations arises.
In other words, the clock signal supplied from outside the device is distributed to all input buffers that buffer address signals and (input) data or various commands. However, there are many of the above input buffers particularly in DRAM embedded logic circuits and therefore, longer wiring is required to transmit the above clock signal. Furthermore, the number of transistors for input buffers to which a clock is supplied increases and the capacity of the gate connected to the clock wiring increases accordingly. This power consumption required for the charge and discharge that drives this capacity then increases.